UNITED STATES
SECURITIES AND EXCHANGE COMMISSION

Washington, D.C. 20549

FORM 10-K

(Mark One)

x                              ANNUAL REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934 FOR THE FISCAL YEAR ENDED DECEMBER 30, 2006

or

o                 TRANSITION REPORT PURSUANT TO SECTION 13 OR 15(d) OF THE SECURITIES EXCHANGE ACT OF 1934

FOR THE TRANSITION PERIOD FROM             TO                  

Commission file number: 000-18032

LATTICE SEMICONDUCTOR CORPORATION

(Exact name of registrant as specified in its charter)

 

Registrant’s telephone number, including area code: (503) 268-8000

Securities registered pursuant to Section 12(b) of the Act:

 

Securities registered pursuant to Section 12(g) of the Act: None

Indicate by check mark if the registrant is a well-known seasoned issuer, as defined in Rule 405 of the Securities Act. Yes o  No x

Indicate by check mark if the registrant is not required to file reports pursuant to Section 13 or Section 15(d) of the Act. Yes o  No x

Indicate by check mark whether the registrant (1) has filed all reports required to be filed by Section 13 or 15(d) of the Securities Exchange Act of 1934 during the preceding 12 months (or for such shorter period that the registrant was required to file such reports), and (2) has been subject to such filing requirements for the past 90 days. Yes x  No o

Indicate by check mark if disclosure of delinquent filers pursuant to Item 405 of Regulation S-K (§229.405 of this chapter) is not contained herein, and will not be contained, to the best of the registrant’s knowledge, in definitive proxy or information statements incorporated by reference in Part III of this Form 10-K or any amendment to this Form 10-K. x

Indicate by check mark whether the registrant is a large accelerated filer, an accelerated filer, or a non-accelerated filer. See definition of  “accelerated filer and large accelerated filer” in Rule 12b-2 of the Exchange Act. (Check one):

 

Indicate by check mark whether the registrant is a shell company (as defined in Rule 12b-2 of the Act). Yes o   No x

 

DOCUMENTS INCORPORATED BY REFERENCE

The information required by Part III of this Report, to the extent not set forth herein, is incorporated herein by reference from the registrant’s definitive proxy statement relating to the 2007 Annual Meeting of Stockholders, which definitive proxy statement shall be filed with the Securities and Exchange Commission within 120 days after the end of the fiscal year to which this Report relates.

LATTICE SEMICONDUCTOR CORPORATION
FORM 10-K
ANNUAL REPORT
TABLE OF CONTENTS

 

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Forward-Looking Statements

This Annual Report on Form 10-K contains forward-looking statements within the meaning of Section 27A of the Securities Act of 1933, as amended, and Section 21E of the Securities Exchange Act of 1934, as amended. Any statements about our expectations, beliefs, plans, objectives, assumptions or future events or performance are not historical facts and may be forward-looking. We use words or phrases such as “anticipates,” “believes,” “estimates,” “expects,” “intends,” “plans,” “projects,” “may,” “will,” “should,” “continue,” “ongoing,” “future,” “potential” and similar words or phrases to identify forward-looking statements.

Forward-looking statements involve estimates, assumptions, risks and uncertainties that could cause actual results to differ materially from those expressed in the forward-looking statements. The key factors that could cause our actual results to differ materially from the forward-looking statements include overall semiconductor market conditions, market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks, and the other risks that are described herein and that are otherwise described from time to time in our filings with the Securities and Exchange Commission (“SEC”), including but not limited to, the items discussed in “Risk Factors” in Item 1A of Part I of this report. You should not unduly rely on forward-looking statements because our actual results could materially differ from those expressed in any forward-looking statements made by us. Further, any forward-looking statement applies only as of the date on which it is made. We are not required to update any forward-looking statement or statements to reflect events or circumstances after the date on which such statement is made or to reflect the occurrence of unanticipated events.

Item 1. Business.

Lattice Semiconductor Corporation (the “Company”) designs, develops and markets high performance programmable logic products and related software. Programmable logic products are widely used semiconductor components that can be configured by end customers as specific logic circuits, and thus enable shorter design cycle times and reduced development costs. Our end customers are primarily original equipment manufacturers in the communications, computing, consumer, industrial, automotive, medical and military end markets.

Lattice was incorporated in Oregon in 1983 and reincorporated in Delaware in 1985. Our principal offices are located at 5555 N.E. Moore Court, Hillsboro, Oregon 97124, our telephone number is (503) 268-8000 and our website can be accessed at www.latticesemi.com. Information contained or referenced on our website is not incorporated by reference into, and does not form a part of, this Annual Report on Form 10-K.

We report based on a 52 or 53-week year ending on the Saturday closest to December 31. Our fiscal 2002, 2004, 2005 and 2006 years were 52-week years and ended December 28, 2002, January 1, 2005, December 31, 2005 and December 30, 2006, respectively. Our 2003 fiscal year was a 53-week year and ended January 3, 2004. All references to quarterly or yearly financial results are references to the results for the relevant fiscal period.

Programmable Logic Market Background

Three principal types of digital integrated circuits are used in most electronic systems: microprocessors, memory and logic. Microprocessors are used for control and computing tasks, memory is used to store programming instructions and data, and logic is employed to manage the interchange and manipulation of digital signals within a system. Logic contains interconnected groupings of simple logical “and” and logical “or” functions, commonly described as “gates.” Typically, complex combinations of individual gates are required to implement the specialized logic functions required for systems.

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Logic circuits are found in a wide range of today’s digital electronic equipment including communications, computing, consumer, industrial, automotive, medical, and military systems. The logic market encompasses general purpose logic semiconductor products, which include programmable logic devices, and application-specific semiconductor products, which include ASICs (devices marketed to a single user) and ASSPs (devices marketed to multiple users). According to Gartner(1), the general purpose logic and application-specific semiconductor product categories combined accounted for approximately 37% of the estimated $259 billion worldwide semiconductor market in 2006. Manufacturers of electronic equipment are challenged to bring differentiated products to market quickly. These competitive pressures often preclude the use of custom-designed ASICs, which generally entail significant design risks, non-recurring costs and time delays. Standard logic products, an alternative to custom designed ASICs, limit a manufacturer’s flexibility to adequately customize an end system. Programmable logic addresses this inherent dilemma. Programmable logic is a standard semiconductor product, purchased by systems manufacturers in a “blank” state, that can be custom configured into a virtually unlimited number of specific logic functions by programming the device with electrical signals. Programmable logic gives system designers the ability to quickly create custom logic functions to provide product differentiation without sacrificing rapid time to market.

According to Gartner(1), the programmable logic market was approximately $3.7 billion in 2006. Within this market, there are two main segments,  field programmable gate arrays (“FPGAs”) and programmable logic devices (“PLDs”), each representing a distinct silicon architectural approach. We believe that in 2006, FPGA was a $3.0 billion market while PLD was a $0.7 billion market. Products based on the two alternative programmable logic architectures are generally optimal for different types of logic functions, although many logic functions can be implemented using either architecture. FPGAs are characterized by a narrow-input logic cell and use a distributed interconnect scheme. FPGAs may also contain dedicated blocks of fixed circuits such as memory, high-speed input/output interface or processors. PLDs are characterized by a regular building block structure of wide-input logic cells, called macrocells, and use a centralized logic interconnect scheme. Although FPGAs and PLDs are typically suited for use in distinct types of logic applications, we believe that a substantial portion of programmable logic customers utilize both FPGA and PLD products.

Lattice Products

We strive to offer innovative and differentiated programmable solutions based on our proprietary technology and intellectual property.

FPGA Products

In 2002, we entered the FPGA market as a result of our acquisition of the Agere FPGA business. During fiscal 2006, 20% of our revenue was derived from FPGA products, as compared to 18% in 2005 and 19% in 2004. In the future, we plan to introduce new families of innovative, high performance FPGAs. The key features of our newest FPGA families are described in the table below:

(1)          Gartner Dataquest, “Semiconductor Forecast Worldwide—Forecast Database,” Nolan Reilly and Richard Gordon, Nov. 15, 2006.

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The LatticeSC family of FPGAs combines a high performance FPGA fabric, with many advanced features in a single unique architecture. This family is fabricated using 90nm technology to provide high performance, and includes specific features to meet the needs of today’s high-speed communication system designs. These features include up to 32 channels of 3.8Gbps serializer/deserializer (“SERDES”) with an advanced embedded Physical Coding Sub-layer (“PCS”), up to 9.6 Mbits of RAM, and dedicated I/O logic to support source synchronous I/O standards such as RapidIO, HyperTransport, SPI4.2, SFI-4, UTOPIA, XGMII and CSIX. Multiple hierarchical clocking and clock management resources are provided to support programmable logic designs needed in today’s high-end system designs. High speed I/O with bandwidths up to 2Gbps per pin are designed for use with high throughput systems. For low cost system level integration, the LatticeSC family offers MACO™ (Masked Array for Cost Optimization) structured ASIC blocks: up to 12 blocks per device with a variety of pre-engineered intellectual property (“IP”) cores.

The LatticeECP2 family integrates features and capabilities previously only available in higher cost/high performance FPGAs; this second generation family expands the range of applications that can take advantage of low cost FPGA products. These integrated features and capabilities include pre-engineered source synchronous I/O for implementation of double data rate (“DDR”) and double data rate two (“DDR2”) memory interfaces, enhanced configuration options, and high performance multiply, addition, subtract and accumulate digital signal processing (“DSP”) blocks.

We also recently introduced the LatticeECP2M FPGA family to serve customers who need low-cost SERDES capability for chip-to-chip and small form-factor backplane applications. The LatticeECP2M family maintains all of the features of the LatticeECP2 family that are required for high-volume, cost-sensitive applications, while providing increased memory capacity (ranging from 1.3 Mbits to 5.5 Mbits) and DSP resources (ranging from 24 to 168 multipliers). The five devices in the series provide an inexpensive alternative for implementing PCI Express, Ethernet, Serial RapidIO and CPRI/OBSAI interfaces. The SERDES integrated into the LatticeECP2M devices has been engineered as a quad-based architecture with 1 to 4 quads (up to a maximum of 16 SERDES channels per device), depending on the size of the device. Each quad features 4 SERDES channels (4 complete TX and RX channels), with each channel typically operating on 100mW at full speed and supporting data rates from 270 Mbps to 3.125 Gbps. A flexible PCS layer that includes 8b/10b encoding, an Ethernet link state machine and rate matching circuitry also are built onto the chip.

The LatticeXP family, introduced in 2005, is a non-volatile FPGA family manufactured using a 130nm embedded flash process co-developed with our foundry partner Fujitsu Limited (“Fujitsu”). Unlike traditional FPGAs that require an external device to load the configuration bitstream, our non-volatile FPGA products embed a flash block on chip to store the bitstream, which offers customers unique benefits with regard to design security, instant-on logic functionality and improved field upgradability.

The LatticeEC/P, introduced in 2004, is a 130nm family currently in volume production. This family was designed to support high volume customer applications, which require a low cost FPGA fabric. Additionally, this family provides several important, performance-enhancing features, including built-in DDR memory support, a flexible high-performance DSP block and support for industry standard, low cost, SPI-flash boot memories.

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PLD Products

During fiscal 2006, 80% of our revenue was derived from PLD products, as compared to 82% in 2005 and 81% in 2004. At present, we offer the industry’s broadest line of PLDs based on our numerous families of ispLSI® , ispMACH™ and GAL® products. The key features of selected PLD families are described in the table below:

 

The MachXO family of crossover programmable logic devices combines an optimized lookup table (“LUT”) fabric with Lattice’s non-volatile technology to provide the high pin-to-pin performance and instant-on logic functionality associated with PLDs, and the flexibility of FPGAs. This low cost, infinitely reconfigurable family is designed to offer a cost effective alternative for applications traditionally served by PLDs or low capacity FPGAs such as bus bridging, bus interface and control.

In addition to high performance, the ispMACH 4000Z family features an architecture optimized to ensure ultra-low power consumption. Devices within this family, targeted toward handheld and portable equipment, typically operate using 10-15 microamps of current while in standby mode.

We also offer the industry’s broadest line of low density PLDs, based on our numerous families of GAL products offered in over 200 speed, power, package and temperature range combinations. These devices range in complexity from approximately 200 to 1,000 logic gates and are typically assembled in 20-, 24- and 28-pin standard dual in-line packages and in 20- and 28-pin standard plastic leaded chip carrier packages. We offer the standard 16V8, 20V8 and 22V10 architectures in a variety of speed grades, with propagation delays as low as 3.5 nanoseconds, the highest performance in the industry.

In addition, we offer the ispPAC® , Power Manager and ispCLOCK™ families of programmable mixed signal devices. These devices, featuring a combination of programmable logic and programmable analog, allow system designers to quickly and easily implement a wide variety of power and clock management functions within a single integrated circuit. Our ispPAC products can replace numerous discrete components while providing customers with additional design flexibility and time-to-market benefits. We believe these devices provide an opportunity to extend our proprietary technology to an untapped potential market.

Software Development Tools and Intellectual Property Cores

Our products are supported by the ispLEVER® software development tool suite and PAC-Designer® software. Supporting Windows, UNIX and LINUX platforms, ispLEVER software allows our customers to enter, verify and synthesize a design, perform logic simulation and timing analysis, assign input/output pins, designate critical paths, debug, execute automatic timing-driven place and route tasks, and download a logic and input/output configuration to our devices. Designed to seamlessly integrate with third-party electronic design automation environments, ispLEVER software provides a front-to-back design flow that leverages a customer’s prior investment in tools offered by Aldec, Altium, Cadence, Mentor Graphics, Synopsys and Synplicity. In the future, we plan to continue to enhance and expand the capability of our software development tool suite.

Lattice’s IP core program (ispLeverCORE™) assists our customers’ design efforts by providing pre-tested, reusable functions that can be easily utilized, allowing our customers to focus on their unique system architectures. These IP cores eliminate the need to “re-invent the wheel,” by providing many industry-standard functions, including PCI, PCIexpress, DDR, Ethernet and embedded microprocessor and related peripherals.

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Product Development

We place substantial emphasis on new product development and believe that continued investment in this area is required to maintain and improve our competitive position. Our product development activities emphasize new proprietary products, enhancement of existing products and process technologies and improvement of software development tools. Product development activities occur in Hillsboro, Oregon; San Jose, California; Downers Grove, Illinois; Bethlehem, Pennsylvania; and Shanghai, China. During 2005, we closed three smaller silicon design centers and one software development center, and consolidated the development activities of those centers into our larger facilities.

Research and development expenses were $82.0 million in fiscal 2006, $97.2 million in 2005 and $94.4 million in 2004. While we expect to continue to make significant future investments in research and development, we streamlined and consolidated our research and development process during the fourth quarter of 2005, the impact of which is reflected in Restructuring charges. (See discussion under “Item 7. Management’s Discussion and Analysis of Financial Condition and Results of Operations”).

Operations

We do not manufacture our own silicon wafers. We maintain strategic relationships with large semiconductor foundries to source our finished silicon wafers. This strategy allows us to focus our internal resources on product and market development, and eliminates the fixed cost of owning and operating semiconductor manufacturing facilities. We are also able to take advantage of the ongoing advanced process technology development efforts of semiconductor foundries. In addition, all of our assembly operations and most of our test operations are performed by outside suppliers. We perform certain test operations and reliability and quality assurance processes internally. We have achieved and maintained ISO 9001 quality certification since 1993, which is an indication of our high internal operational standards. In 2006, we achieved ISO/TS16949:2002 Quality Systems Certification, and released a full line of PLD products qualified to the AEC-Q100 Reliability Standard.

Wafer Fabrication

We source silicon wafers from our foundry partners, Fujitsu in Japan, Seiko Epson in Japan, United Microelectronics Corporation (“UMC”) in Taiwan and Chartered Semiconductor Manufacturing, Ltd. (“Chartered Semiconductor”) in Singapore, pursuant to agreements with each company and their respective affiliates. We negotiate wafer volumes, prices and other terms with our foundry partners and their respective affiliates on a periodic basis.

Assembly

After wafer fabrication and initial testing, we ship wafers to independent subcontractors for assembly. During assembly, wafers are separated into individual die and encapsulated in plastic or ceramic packages. Presently, we have qualified assembly partners in China, Indonesia, Japan, Malaysia, the Philippines and South Korea. We negotiate assembly prices, volumes and other terms with our assembly partners and their respective affiliates on a periodic basis.

We currently offer an extensive list of standard products in lead (Pb) free packaging. Our lead-free products meet the European Parliament Directive entitled “Restrictions on the use of Hazardous Substances.” We continually review our suppliers to ensure they meet or exceed our packaging requirements.

Testing

We electrically test the die on each wafer prior to shipment for assembly. Following assembly, prior to customer shipment, each product undergoes final testing and quality assurance procedures. Final testing

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on certain products is performed by independent contractors in China, Indonesia, Japan, Malaysia, the Philippines and South Korea, and at our Oregon facility.

Marketing, Sales and Customers

We sell our products directly to end customers through a network of independent manufacturers’ representatives and indirectly through a network of independent distributors. We also employ a direct sales management and field applications engineering organization to support our end customers and indirect sales resources. Our end customers are primarily original equipment manufacturers in the communications, computing, consumer, industrial, automotive, medical and military end markets.

As of December 2006, we have agreements with 20 manufacturers’ representatives and two primary distributors, Arrow Electronics, Inc. and Avnet Inc., in North America. We have also established export sales channels in over 50 foreign countries through a network of over 30 sales representatives and distributors. The majority of our sales are made through distributors.

We protect both of our primary North American distributors and some of our foreign distributors against reductions in published prices, and expect to continue this policy in the foreseeable future. We also allow returns from these distributors of unsold products under certain conditions. For these reasons, we do not recognize revenue until products are resold by these distributors to an end customer.

We provide technical and marketing support to our end customers with engineering staff based at our headquarters, product development centers and selected field sales offices. We maintain numerous domestic and international field sales offices in major metropolitan areas.

Export sales as a percentage of our total revenue were 80% in fiscal 2006, 77% in 2005 and 71% in 2004. Export sales to China were 17% of revenue in fiscal 2006 and 13% in both 2005 and 2004, while export sales to Japan were 13% of revenue in fiscal 2006, 15% of revenue in 2005 and 14% of revenue in 2004. In addition, export sales to Taiwan were 11% of revenue in fiscal 2006, eight percent in 2005 and nine percent in 2004. Both export and domestic sales are denominated in U.S. dollars, with the exception of sales to Japan, which are denominated in yen. If our export sales decline significantly, there would be a material adverse impact on our business and results of operations.

Our products are sold to a large and diverse group of customers. No individual end customer accounted for more than 10% of total revenue in any of fiscal years 2006, 2005 or 2004.

Seasonality

In most years, we experience some seasonal trends in the sale of our products. Sales of our products are often stronger in the first half of the year, and often weaker in the summer months. In addition, December is often a weak month for sales. However, on balance, general economic and semiconductor market conditions have a greater impact on our business and financial results than seasonal trends.

Backlog

Our backlog of scheduled and released orders at December 30, 2006 was $45.7 million, as compared to $35.5 million at December 31, 2005. This backlog consisted of direct customer and distributor orders scheduled for delivery within the next 90 days. Distributor orders accounted for the majority of the backlog in both periods. Direct customer orders may be changed, rescheduled or cancelled under certain circumstances without penalty prior to shipment. Additionally, distributor orders generally may be changed, rescheduled or cancelled without penalty prior to shipment. Furthermore, certain of our distributor shipments are subject to rights of return and price adjustment. Revenue associated with these distributor shipments is not recognized until the product is resold to an end customer. Typically, the majority of our revenue results from orders placed and filled within the same period. Such orders are referred to as “turns orders.”  By definition, turns orders are not captured in a backlog measurement made

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at the beginning of a period. We do not anticipate a significant change in this business pattern. For these reasons, backlog as of any particular date should not be used as a predictor of revenue for any future period.

Competition

The semiconductor industry is intensely competitive and characterized by rapid rates of technological change, product obsolescence and price erosion. Our current and potential competitors include a broad range of semiconductor companies from emerging companies to large, established companies, many of which have greater financial, technical, manufacturing, marketing and sales resources than we do.

The principal competitive factors in the programmable logic market include silicon and software product features, price, technical support, and sales, marketing and distribution strength. The availability of competitive intellectual property cores is also critical. In addition to product features such as density, performance, power consumption, reprogrammability, and reliability, competition occurs on the basis of price and market acceptance of specific products and technology. We intend to continue to address these competitive factors by working to continually introduce product enhancements and new products and by working to reduce the manufacturing cost of our products.

We compete directly with Actel Corporation, Altera Corporation and Xilinx, Inc. We also indirectly compete with other semiconductor companies that provide logic solutions that are not user programmable. Although to date we have not experienced direct competition from companies located outside the United States, such companies may become a more significant competitive factor in the future. Competition may also increase if other larger semiconductor companies seek to expand into our market. Any such increases in competition could have a material adverse effect on our operating results.

Patents

We seek to protect our products and technologies primarily through patents, trade secrecy measures, copyrights, mask work protection, trademark registrations, licensing restrictions, confidentiality agreements and other approaches designed to protect proprietary information. There can be no assurance that others may not independently develop competitive technology not covered by our intellectual property rights or that measures we take to protect our technology will be effective.

We hold numerous domestic, European and Asian patents and have patent applications pending in the United States, Asia and Europe. Our current patents will expire at various times between 2007 and 2025. There can be no assurance that pending patent applications or other applications that may be filed will result in issued patents, or that any issued patents will survive challenges to their validity. Although we believe that our patents have value, there can be no assurance that our patents, or any additional patents that may be issued in the future, will provide meaningful protection from competition. We believe that our success will depend primarily upon the technical expertise, experience, creativity and the sales and marketing abilities of our personnel.

Patent and other proprietary rights infringement claims are common in our industry. There can be no assurance that, with respect to any claim made against us, we could obtain a license on terms or under conditions that would not harm our business.

Licenses and Agreements

Advanced Micro Devices

In 1999, as part of our acquisition of Vantis Corporation, a wholly owned subsidiary of Advanced Micro Devices, Inc. (“AMD”), we entered into an agreement with AMD pursuant to which we have cross-licensed Vantis patents with AMD patents, having an effective filing date on or before June 15, 1999, related to programmable logic products. This cross-license was made on a worldwide, non-exclusive and

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royalty-free basis. Additionally, as part of our acquisition of Vantis, we acquired certain third-party license rights held by Vantis prior to the acquisition, including rights to use certain Xilinx patents to manufacture, market and sell products.

Agere Systems

In 2002, as part of our acquisition of the FPGA business of Agere, we entered into an intellectual property agreement with Agere and Agere Systems Guardian Corporation. Pursuant to this agreement, these Agere companies assigned or licensed to us certain FPGA and Field Programmable System Chip patents, trademarks, software and other intellectual property rights and technology, and we licensed back rights in these same assets. These cross-licenses were made on a worldwide and royalty-free basis.

Altera

In 2001, we entered into a comprehensive, royalty-free patent cross-license agreement and a multi-year patent peace agreement with Altera.

Fujitsu

On September 10, 2004, we entered into an Advance Payment and Purchase Agreement (the “Fujitsu APP Agreement”) with Fujitsu Limited (“Fujitsu”), pursuant to which we advanced $125.0 million to Fujitsu in support of the development and construction of a 300mm wafer fabrication facility in Mie, Japan. The initial two payments of $25.0 million each were made in October 2004 and January 2005, and a third payment of $37.5 million was made in November 2006. The final payment of $37.5 million was accrued and recorded at December 30, 2006 and was paid in January 2007.

During the third quarter of fiscal 2006, we entered into an amendment (“Amendment”) to the Fujitsu APP Agreement. Prior to the Amendment, our $125.0 million advance was to be credited against the purchase price of 300mm wafers received from Fujitsu. The Amendment permits us to also credit the advance against the purchase price of 200mm wafers. The Fujitsu APP Agreement will continue until the full amount of the advance payment has been returned to us in the form of wafer credits or other repayment, subject to the right of either party to terminate the agreement upon the occurrence of certain events. Prior to the Amendment, we could request a refund of the unused amount of the advance payment if we have not used all of our wafer credits by December 31, 2007. Pursuant to the Amendment, we may request a refund of the unused amount of the advance payment if we have not used all of our wafer credits by December 31, 2008. The repayment obligation of Fujitsu is unsecured.

Seiko Epson/Epson Electronics America

Epson Electronics America, Inc. (“EEA”), an affiliated U.S. distributor of Seiko Epson, has agreed to provide us with manufactured wafers in quantities based on six-month rolling forecasts. Prices for the wafers obtained from EEA are reviewed and adjusted periodically. Wafers for our products are manufactured in Japan at Seiko Epson’s wafer fabrication facilities and are delivered to us by EEA.

In 1997 we entered into an advance production payment agreement with Seiko Epson and EEA which was subsequently amended in 2002 and March 2004. Under this agreement we advanced $51.3 million to Seiko Epson to finance construction of an eight-inch sub-micron semiconductor wafer manufacturing facility. As of December 30, 2006 all of the payments have been repaid to us in the form of semiconductor wafers. We are not obligated to make additional payments under this agreement.

UMC Group

In 1995, we entered into a series of agreements with United Microelectronics Corporation (“UMC”), a public Taiwanese company, pursuant to which we agreed to join UMC and several other companies to

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form a separate Taiwanese corporation, (“UICC”), for the purpose of building and operating an advanced semiconductor manufacturing facility in Taiwan, China. Under the terms of the agreements, we invested $49.7 million for an approximate 10% equity interest in the corporation and the right to receive a percentage of the facility’s wafer production at market prices.

In 1996, we entered into an agreement with Utek Corporation (“Utek”), a public Taiwanese company in the wafer foundry business that became affiliated with the UMC group in 1998, pursuant to which we agreed to make a series of equity investments in Utek under specific terms. In exchange for these investments, we received the right to purchase a percentage of Utek’s wafer production. Under this agreement, we invested $17.5 million. On January 3, 2000, UICC and Utek merged into UMC.

For financial reporting purposes, all of our shares of UMC common stock are accounted for as available-for-sale and marked to market in our Consolidated Balance Sheet until they are sold, at which time a gain or loss is recognized in our Consolidated Statement of Operations. Unrealized gains and losses are included in Accumulated other comprehensive (loss) income within Stockholders’ equity. An other than temporary impairment of UMC share value could result in a reduction of the Consolidated Balance Sheet carrying value and would result in a charge to our Consolidated Statement of Operations.

Employees

At December 30, 2006, we had 960 full-time employees. We believe that our future success will depend, in part, on our ability to continue to attract and retain highly skilled technical and management personnel. No employee is subject to a collective bargaining agreement. We have never experienced a work stoppage and consider our employee relations to be good.

Executive Officers of the Registrant

The following individuals currently serve as our executive officers:

 

Stephen A. Skaggs joined the Company in December 1992 as Director, Corporate Development. He was appointed Senior Vice President, Chief Financial Officer and Secretary in August 1996. He was appointed President in October 2003, Chief Executive Officer in August 2005 and Director in November 2005.

Jan Johannessen rejoined the Company in October 2001 as Vice President, Investments. In October 2003, he was appointed Corporate Vice President and Chief Financial Officer. He originally joined the Company in 1983 and served as Vice President and Chief Financial Officer between 1987 and 1993. From 1993 to 2001, he worked as an independent venture capitalist. He was appointed Senior Vice President in November 2005.

Martin R. Baker joined the Company in January 1997 as Vice President and General Counsel. He was appointed Secretary in August 2005 and Corporate Vice President in November 2005. From 1991 until he joined the Company, Mr. Baker held legal positions with Altera Corporation.

Stephen M. Donovan joined the Company in October 1989 and served as Director of Marketing and Director of International Sales. He was appointed Vice President, International Sales in August 1993. He was promoted to Corporate Vice President, Sales in May 1998. Mr. Donovan has worked in the programmable logic industry since 1982.

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Available Information

We make available, free of charge through our website at www.latticesemi.com, via a link to the SEC’s website at www.sec.gov, our annual reports on Form 10-K, quarterly reports on Form 10-Q, current reports on Form 8-K, proxy statements and amendments to those reports and statements as soon as reasonably practicable after such materials are electronically filed with, or furnished to, the SEC. You may also obtain free copies of these materials by contacting our Investor Relations Department at 5555 N.E. Moore Court, Hillsboro, Oregon 97124-6421, telephone (503) 268-8000.

Item 1A. Risk Factors.

The following risk factors and other information included in this Annual Report should be carefully considered. The risks and uncertainties described below are not the only ones we face. Additional risks and uncertainties not presently known to us or that we currently deem immaterial also may impair our business operations. If any of the following risks occur, our business, financial condition, operating results, and cash flows could be materially adversely affected.

The cyclical nature of the semiconductor industry may limit our ability to maintain revenue levels and operating results during industry downturns.

The semiconductor industry is highly cyclical, to a greater extent than other less technology-driven industries. Our financial performance has periodically been negatively affected by downturns in the semiconductor industry. Factors that contribute to these industry downturns include:

·       the cyclical nature of the demand for the products of semiconductor customers;

·       general reductions in inventory levels by customers;

·       excess production capacity;

·       general decline in end-user demand; and

·       accelerated declines in average selling prices.

Historically, the semiconductor industry has experienced periodic downturns of varying degrees of severity and duration. Typically, after such downturns, semiconductor industry conditions improve, although such improvement may not be significant or sustainable. Increased demand for semiconductor industry products may not proportionately increase demand for programmable logic products in general, or our products in particular. Even if demand for our products increases, average selling prices for our products may not increase, and could decline. Whenever adverse semiconductor industry conditions or other similar conditions exist, there is likely to be an adverse effect on our operating results.

Further, our ability to predict end-user demand is limited. Typically, the majority of our revenue comes from “turns orders,” which are orders placed and filled within the same quarter. By definition, turns orders are not captured in a backlog measurement at the beginning of a quarter. Accordingly, we cannot use backlog as a reliable measure of predicting revenue.

A downturn in the communications equipment end market or computing end market could cause a reduction in demand for our products and limit our ability to maintain revenue levels and operating results.

The majority of our revenue is derived from customers in the communications equipment and computing end markets. Any deterioration in these end markets or any reduction in technology capital spending could lead to a reduction in demand for our products. For example, in the past, a general weakening in demand for programmable logic products from customers in the communications end market

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has adversely affected our revenue. Whenever adverse economic or end market conditions exist, there is likely to be an adverse effect on our operating results.

We may be unsuccessful in defining, developing or selling the new FPGA products required to maintain or expand our business.

As a semiconductor company, we operate in a dynamic environment marked by rapid product obsolescence. The programmable logic market is characterized by rapid technology and product evolution and historically the market for FPGA products has grown faster than the market for PLD products. Currently we derive a greater proportion of our revenue from PLD products than FPGA products. Consequently, our future success depends on our ability to introduce new FPGA and associated software design tool products that meet evolving customer needs while achieving acceptable margins. We are presently shipping our next generation FPGA product families that are critical to our ability to grow our FPGA product revenue and expand our overall revenue. We also plan to continue upgrading our customer design tool products and increase our offerings of intellectual property cores. If we fail to introduce new products in a timely manner, or if these products or future new products fail to achieve market acceptance, our operating results would be harmed.

Fujitsu has agreed to manufacture our current and future FPGA products on its 130 nanometer and 90 nanometer CMOS process technologies, as well as on 130 nanometer and 90 nanometer technologies with embedded flash memory that we have jointly developed with Fujitsu. We have access to 65 nanometer CMOS process technology from Fujitsu. Fujitsu is our sole source supplier for our newest FPGA products, our new wafer fabrication processes and our planned future FPGA products. The success of our next generation FPGA products is dependent on our ability to successfully partner with Fujitsu. If for any reason we are unsuccessful in our efforts to partner with Fujitsu in connection with these next generation FPGA products, our future revenue growth would be materially adversely affected.

The introduction of new silicon and software design tool products in a dynamic market environment presents significant business challenges. Product development commitments and expenditures must be made well in advance of product sales. The market reception of new products depends on accurate projections of long-term customer demand, which by their nature are uncertain.

Our future revenue growth is dependent on market acceptance of our new silicon and software design tool products and the continued market acceptance of our current products. The success of these products is dependent on a variety of specific technical factors including:

·       successful product definition;

·       timely and efficient completion of product design;

·       timely and efficient implementation of wafer manufacturing and assembly processes;

·       product performance;

·       product cost; and

·       the quality and reliability of the product.

If, due to these or other factors, our new silicon and software products do not achieve market acceptance, our operating results would be harmed.

The potential impact of customer design-in activity on future revenue is inherently uncertain and could impact our ability to manage production or our ability to forecast sales.

We face uncertainties relating to the potential impact of customer design-in activity because it is unknown whether any particular customer design-in will ultimately result in sales of significant volume. After a specific customer design-in is obtained, many factors can impact the timing and amount of sales

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that are ultimately realized from the specific customer design-in. Changes in the competitive position of our technology, our customer’s product competitiveness, our customer’s product strategy, the financial position of our customer, and many other factors can all impact the timing and amount of sales ultimately realized from any specific customer design-in. As a result, we may not be able to accurately manage the production levels of our new products or accurately forecast the future sales of such products, and, thus, our operating results could be harmed.

Our products may not be competitive if we are unsuccessful in migrating our manufacturing processes to more advanced technologies or alternative fabrication facilities.

To develop new products and maintain the competitiveness of existing products, we need to migrate to more advanced wafer manufacturing processes that use smaller device geometries. We also may need to use additional foundries. Because we depend upon foundries to provide their facilities and support for our process technology development, we may experience delays in the availability of advanced wafer manufacturing process technologies at existing or new wafer fabrication facilities. As a result, volume production of our advanced process technologies at fabrication facilities may not be achieved. This could harm our operating results.

Our wafer supply could be interrupted or reduced, which may result in a shortage of products available for sale.

We do not manufacture finished silicon wafers and many of our products, including all of our newest FPGA products, are manufactured by a sole source. Currently, our silicon wafers are manufactured by Fujitsu in Japan, Seiko Epson in Japan, UMC in Taiwan and Chartered Semiconductor in Singapore. If any of our current or future foundry partners significantly interrupts or reduces our wafer supply, our operating results could be harmed.

In the past, we have experienced delays in obtaining wafers and in securing supply commitments from our foundries. At present, we anticipate that our supply commitments are adequate. However, these existing supply commitments may not be sufficient for us to satisfy customer demand in future periods. Additionally, notwithstanding our supply commitments, we may still have difficulty in obtaining wafer deliveries consistent with the supply commitments. We negotiate wafer prices and supply commitments from our suppliers on at least an annual basis. If any of our foundry partners were to reduce its supply commitment or increase its wafer prices, and we cannot find alternative sources of wafer supply, our operating results could be harmed.

Many other factors that could disrupt our wafer supply are beyond our control. Since worldwide manufacturing capacity for silicon wafers is limited and inelastic, we could be harmed by significant industry-wide increases in overall wafer demand or interruptions in wafer supply. Additionally, a future disruption of any of our foundry partners’ foundry operations as a result of a fire, earthquake, act of terrorism, political unrest, governmental uncertainty, war, or other natural disaster or catastrophic event could disrupt our wafer supply and could harm our operating results.

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If our foundry partners experience quality or yield problems, we may face a shortage of products available for sale.

We depend on our foundries to deliver high quality silicon wafers with acceptable yields in a timely manner. As is common in our industry, we have experienced wafer yield problems and delivery delays. If our foundries are unable for a prolonged period to produce silicon wafers that meet our specifications, with acceptable yields, our operating results could be harmed.

The reliable manufacture of high performance programmable logic devices is a complicated and technically demanding process requiring:

·       a high degree of technical skill;

·       state-of-the-art equipment;

·       the availability of certain basic materials and supplies, such as chemicals, gases, polysilicon, silicon wafers and ultra-pure metals;

·       the absence of defects in production wafers;

·       the elimination of minute impurities and errors in each step of the fabrication process; and

·       effective cooperation between the wafer supplier and us.

As a result, our foundries may experience difficulties in achieving acceptable quality and yield levels when manufacturing our silicon wafers.

Our supply of assembled and tested products could be interrupted or reduced, which may result in a shortage of products available for sale.

We do not assemble our finished products or perform all testing of our products. Currently, our finished products are assembled and tested by ASE in Malaysia, Amkor in the Philippines and South Korea, Fujitsu in Japan, AIT in Indonesia, and other independent contractors in Asia. If any of our current or future assembly or test contractors significantly interrupts or reduces our supply of assembled and tested devices, our operating results could be harmed.

In the past, we have experienced delays in obtaining assembled and tested products and in securing assembly and test capacity commitments from our suppliers. At present, we anticipate that our assembly and test capacity commitments are adequate. However, these existing commitments may not be sufficient for us to satisfy customer demand in future periods. Additionally, notwithstanding our assembly and test capacity commitments we may still have difficulty in obtaining deliveries of finished products consistent with the capacity commitments. We negotiate assembly and test prices and capacity commitments from our contractors on a periodic basis. If any of our assembly or test contractors were to reduce its capacity commitment or increase its prices, and we cannot find alternative sources, our operating results could be harmed.

Many other factors that could disrupt our supply of finished products are beyond our control. Since worldwide capacity for assembly and testing of semiconductor products is limited and inelastic, we could be harmed by significant industry-wide increases in overall demand or interruptions in supply. The assembly of complex packages requires a consistent supply of a variety of raw materials such as substrates, leadframes, and mold compound. The worldwide manufacturing capacity for these materials is also limited and inelastic. A significant industry-wide increase in demand, or interruptions in the supply of these materials to our assembly or test contractors, could harm our operating results. Additionally, a future disruption of any of our assembly or test contractors’ operations as a result of a fire, earthquake, act of terrorism, political unrest, governmental uncertainty, war, or other natural disaster or catastrophic event could disrupt our supply of assembled and tested devices and could harm our operating results.

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In addition, our quarterly revenue levels may be affected to a significant extent by our ability to match inventory and current production mix with the product mix required to fulfill orders. The large number of individual parts we sell and the large number of customers for our products, combined with limitations on our and our customer’s ability to forecast orders accurately and our relatively lengthy manufacturing cycles, may make it difficult to achieve a match of inventory on hand, production units, and shippable orders sufficient to realize quarterly or annual revenue projections.

If our assembly and test supply contractors experience quality or yield problems, we may face a shortage of products available for sale.

We rely on contractors to assemble and test our devices with acceptable quality and yield levels. As is common in our industry, we have experienced quality and yield problems in the past. If we experience prolonged quality or yield problems in the future, our operating results could be harmed.

The majority of our revenue is derived from semiconductor devices assembled in advanced packages. The assembly of advanced packages is a complex process requiring:

·       a high degree of technical skill;

·       state-of-the-art equipment;

·       the absence of defects in assembly and packaging manufacturing;

·       the elimination of raw material impurities and errors in each step of the process; and

·       effective cooperation between the assembly contractor and us.

As a result, our contractors may experience difficulties in achieving acceptable quality and yield levels when assembling and testing our semiconductor devices.

Product quality problems could lead to reduced revenue, gross margins, and net income.

We generally warrant our products for varying lengths of time against non-conformance to our specifications and certain other defects. Because our products, including hardware and software, are highly complex and incorporate leading-edge technology, our quality assurance programs may not detect all defects, whether manufacturing defects in individual products or systematic defects that could affect numerous shipments. On occasion we have repaired or replaced certain components and software or refund the purchase price or license fee paid by our customers due to product defects. If there are material increases in warranty claims or the costs to resolve warranty claims compared with our historical experience, our revenue, gross margins, and net income may be adversely affected. For example, an inability to cure a product defect in a timely manner could result in product reengineering expenses, increased inventory costs, or damage to our reputation, any of which could materially impact our revenue, gross margins, and net income.

Conditions in Asia may disrupt our existing supply arrangements and result in a shortage of finished products available for sale.

All of our major silicon wafer suppliers operate fabrication facilities located in Asia. Additionally, our finished silicon wafers are assembled and tested by independent contractors located in China, Indonesia, Japan, Malaysia, the Philippines and South Korea. Economic, financial, social and political conditions in Asia have historically been volatile. Financial difficulties, the effects of currency fluctuation, governmental actions or restrictions, prolonged work stoppages, political unrest, war, natural disaster, disease or any other difficulties experienced by our suppliers may disrupt our supply and could harm our operating results.

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Export sales account for the majority of our revenue and may decline in the future due to economic and governmental uncertainties.

We derive a majority of our revenue from export sales. Accordingly, if we experience a decline in export sales, our operating results could be harmed. Our export sales are subject to numerous risks, including:

·       changes in local economic conditions;

·       exchange rate volatility;

·       governmental controls and trade restrictions;

·       export license requirements and restrictions on the export of technology;

·       political instability, war or terrorism;

·       changes in tax rates, tariffs or freight rates;

·       interruptions in air transportation; and

·       difficulties in staffing and managing foreign sales offices.

We may not be able to successfully compete in the highly competitive semiconductor industry.

The semiconductor industry is intensely competitive and many of our direct and indirect competitors have substantially greater financial, technological, manufacturing, marketing and sales resources. If we are unable to compete successfully in this environment, our future results will be adversely affected.

The current level of competition in the programmable logic market is high and may increase in the future. We currently compete directly with companies that have licensed our technology or have developed similar products. We also compete indirectly with numerous semiconductor companies that offer products based on alternative technical solutions. These direct and indirect competitors are established multinational semiconductor companies as well as emerging companies.

We may fail to retain or attract the specialized technical and management personnel required to successfully operate our business.

To a greater degree than most non-technology companies or larger technology companies, our future success depends on our ability to attract and retain highly qualified technical and management personnel. As a mid-sized company, we are particularly dependent on a relatively small group of key employees. Competition for skilled technical and management employees is intense within our industry. As a result, we may not be able to retain our existing key technical and management personnel. In addition, we may not be able to attract additional qualified employees in the future. If we are unable to retain existing key employees or are unable to hire new qualified employees, our operating results could be adversely affected.

We may have failed to adequately insure against certain risks, and, as a result, our financial condition and results may be adversely affected.

We carry insurance customary for companies in our industry, including, but not limited to, liability, property and casualty, worker’s compensation and business interruption insurance. We also self-insure our employees for basic medical expenses, subject to a true insurance stop loss for catastrophic illness. In addition, we have insurance contracts that provide director and officer liability coverage for our directors and officers. Other than the specific areas mentioned above, we are self-insured with respect to most other risks and exposures, and the insurance we carry in many cases is subject to a significant policy deductible or other limitation before coverage applies. Based on management’s assessment and judgment, we have

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determined that it is more cost effective to self-insure against certain risks than to incur the insurance premium costs. The risks and exposures for which we self-insure include, but are not limited to, natural disasters, product defects, political risk, theft, patent infringement and some employment practice matters. Should there be a catastrophic loss due to an uninsured event such as an earthquake or a loss due to adverse occurrences in any area in which we are self-insured, our financial condition, results of operations and liquidity may be adversely affected.

Changes in accounting for equity compensation will adversely affect our consolidated statement of operations and could adversely affect our ability to attract and retain employees.

We have historically used equity incentives as a key component of employee compensation in order to align employees’ interests with the interests of our stockholders, encourage employee retention, and provide competitive compensation packages.  The Financial Accounting Standards Board has adopted changes to generally accepted accounting principles that require us and other companies to record a charge to earnings for employee stock option grants and other equity incentives beginning in the quarter ended April 1, 2006. To the extent that these or other new regulations make it more difficult or expensive to grant stock options and other equity incentives to employees, we will incur increased compensation costs. We may also change our equity compensation strategy, and this could make it difficult to attract, retain and motivate employees. Any of these results could materially and adversely affect our business.

If we are unable to effectively and efficiently improve our internal controls in response to changing business, accounting and regulatory factors there could be a material adverse effect on our operations or financial results.

No assurance can be given that we will be able to successfully maintain, change and enhance as appropriate, our internal controls and procedures, or that any changes or enhancements to our controls and procedures will have the desired effect. In addition, we may be required to hire additional employees, and may experience higher than anticipated capital expenditures and operating expenses, during the implementation of any changes and enhancements and thereafter. Furthermore, future assessments of our internal controls and procedures may reveal material weaknesses. If we are unable to maintain, and effectively and efficiently change and enhance as appropriate, our internal controls and procedures, or if we discover material weaknesses, there could be a material adverse effect on our operations or financial results.

If we are unable to adequately protect our intellectual property rights, our financial results and competitive position may suffer.

Our success depends in part on our proprietary technology. However, we may fail to adequately protect this technology. As a result, we may lose our competitive position or face significant expense to protect or enforce our intellectual property rights.

We intend to continue to protect our proprietary technology through patents, copyrights and trade secrets. Despite this intention, we may not be successful in achieving adequate protection. Claims allowed on any of our patents may not be sufficiently broad to protect our technology. Patents issued to us also may be challenged, invalidated or circumvented. Finally, our competitors may develop similar technology independently.

Companies in the semiconductor industry vigorously pursue their intellectual property rights. If we become involved in protracted intellectual property disputes or litigation we may be forced to use substantial financial and management resources, which could have an adverse effect on our operating results.

Our industry is characterized by frequent claims regarding patents and other intellectual property rights of others. We have been, and from time to time expect to be, notified of claims that we are infringing

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the intellectual property rights of others. If any third party makes a valid claim against us, we could face significant liability and could be required to make material changes to our products and processes. In response to any claims of infringement, we may seek licenses under patents that we are alleged to be infringing. However, we may not be able to obtain a license on favorable terms, or at all, without our operating results being adversely affected.

We face risks related to litigation.

We are exposed to certain asserted and unasserted potential claims. There can be no assurance that, with respect to potential claims made against us, we could resolve such claims under terms and conditions that would not have a material adverse effect on our business, our liquidity or our financial results. We have been and may in the future be subject to various other legal proceedings, including, as discussed in greater detail hereafter, claims that involve possible infringement of patent and other intellectual property rights of third parties. It is inherently difficult to assess the outcome of litigation matters, and there can be no assurance that we will prevail in any litigation. Any such litigation could result in a substantial diversion of our efforts and the use of substantial management and financial resources, which by itself could have a material adverse effect on our financial condition and operating results. Further, an adverse determination in any such litigation could result in a material adverse impact on our financial position and the results of operations for the period in which the effect of an unfavorable final outcome becomes probable and reasonably estimable.

Our future quarterly operating results may fluctuate and therefore may fail to meet expectations.

Our quarterly operating results have fluctuated in the past and may continue to fluctuate. Consequently, our operating results may fail to meet the expectations of analysts and investors. As a result of industry conditions and the following specific factors, our quarterly operating results are more likely to fluctuate and are more difficult to predict than a typical non-technology company of our size and maturity:

·       general economic conditions in the countries where we sell our products;

·       conditions within the end markets into which we sell our products;

·       the cyclical nature of demand for our customers’ products;

·       excessive inventory accumulation by our end customers;

·       the timing of our and our competitors’ new product introductions;

·       product obsolescence;

·       the scheduling, rescheduling and cancellation of large orders by our customers;

·       the willingness and ability of our customers and distributors to make payment to us in a timely manner;

·       our ability to develop new process technologies and achieve volume production at wafer fabrication facilities;

·       changes in manufacturing yields including delays in achieving target yields on new products;

·       adverse movements in exchange rates, interest rates or tax rates; and

·       the availability of adequate supply commitments from our wafer foundries and assembly and test subcontractors.

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Our stock price may continue to experience large fluctuations.

Historically, the price of our common stock has at times experienced rapid and severe price fluctuations that have left investors little time to react. The price of our common stock may continue to fluctuate greatly in the future due to a variety of company specific factors, including:

·       quarter-to-quarter variations in our operating results;

·       shortfalls in revenue or earnings from levels expected by investors;

·       announcements of technological innovations or new products by other companies; and

·       any developments that materially adversely impact investors’ perceptions of our business prospects.

At December 30, 2006, our book value per share was $4.45 compared to our stock price, which has ranged from a low of $4.20 per share to a high of $7.55 per share for fiscal 2006. Presently, our stock price is trading above our consolidated book value. Should our stock price drop below book value for a sustained period, it may become necessary to record an impairment charge to goodwill, which would negatively impact our results of operations.

Item 1B. Unresolved Staff Comments.

None.

Item 2. Properties.

Our corporate headquarters consists of land and 200,000 square feet of buildings we own in Hillsboro, Oregon. A portion of undeveloped land near the corporate headquarters is currently marketed for sale. In China, we own 19,000 square feet of research and development space and lease an additional 8,000 square feet of research and development space in a facility in Shanghai. We also own a 14,000 square foot facility in Shanghai, China that is vacant. We are currently seeking to lease or sell this facility. We currently lease a 133,000 square foot research and development facility in San Jose, California through December 2008, a 6,400 square foot research and development facility in Illinois through August 2007, and a 36,000 square foot research and development facility in Pennsylvania through August 2009. We also lease office facilities in multiple metropolitan locations for our domestic and international sales staff. We believe that our existing facilities are suitable and adequate for our current and foreseeable future needs.

Additionally, we lease a 25,000 square foot facility in Austin, Texas through December 2011, a 7,500 square foot facility in the United Kingdom through December 2013 and a 6,300 square foot facility in Colorado through December 2007. As part of our 2005 restructuring plan (see discussion under “Item 7. Management’s Discussion and Analysis of Financial Condition and Results of Operations”) in December 2005 we ceased our research and development operations in these three locations, and have subleased the Colorado facility through the end of 2007. We are currently seeking to sublease the premises in the United Kingdom.

In the first quarter of 2007 we entered into a sublease agreement for a portion of the research and development facility in San Jose, California, and for the vacated premises in Austin, Texas.

Item 3. Legal Proceedings.

In September and October 2004, three putative class action complaints were filed in the United States District Court for the District of Oregon against Lattice Semiconductor Corporation, our Chief Executive Officer and President Stephen A. Skaggs, and our former Chief Executive Officer Cyrus Y. Tsui. These complaints were filed on behalf of a putative class of investors who purchased our stock between April 22, 2003 and April 19, 2004. They generally alleged violations of federal securities laws arising out of our previously announced restatement of financial results for the first, second, and third quarters of 2003.

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Consistent with the usual procedures for cases of this kind, these cases were amended and consolidated into a single action. In an amended and consolidated complaint filed January 27, 2005 our former President and our former Controller were added as defendants. The complaints generally sought an unspecific amount of damages, as well as attorney fees and costs. On March 16, 2006 the Company announced it had entered into an agreement with the plaintiffs to settle the consolidated action. The agreement does not contain any admission of fault or wrongdoing on the part of the Company or any of the individual defendants in the litigation, and provides that plaintiffs will receive an aggregate amount of $3.5 million, inclusive of fees and expenses of counsel, in exchange for a release of the Company and the individual defendants from all claims asserted in the litigation. The Company’s insurance carriers have paid the entire amount, on behalf of the Company, to settle the suit under the terms of the Company’s director and officer liability insurance policy. On November 6, 2006, the court formally approved the settlement and issued an Order of Dismissal with Prejudice. The Company had previously recorded a liability in its financial statements for the proposed amount of the settlement. Additionally, because the insurance carriers had agreed to pay the entire $3.5 million settlement amount, a receivable was also recorded for the same amount. Accordingly, there was no impact to the Consolidated Statement of Operations as the amounts of the settlement and the insurance recovery fully offset. With the final settlement and dismissal of the litigation with prejudice, the offsetting receivable and liability have been reversed as of December 30, 2006.

We previously announced that the SEC had been conducting an informal inquiry into our restatement of financial results for the first, second, and third quarters of 2003. We also previously announced that our Audit Committee conducted an internal examination concerning issues primarily associated with executive compensation and several items pertaining to our internal controls. We have furnished information regarding our restatement and the other matters examined by the Audit Committee to the SEC. On September 30, 2005 the SEC issued a Cease-and-Desist Order concerning our former Controller, and referenced certain events in connection with our prior restatement of financial results. In September 2006, we made a settlement offer to the SEC to resolve the informal inquiry. We offered to consent to the entry of a cease and desist order with respect to violations of Sections 13(a) and 13(b)(2)(A)-(B) of the Securities Exchange Act of 1934, as amended, and Rule 13a-13 promulgated thereunder. The proposed settlement was approved by the SEC, and on January 12, 2007 the SEC issued an Order instituting Cease-and-Desist Proceedings, making findings, and imposing a Cease-and-Desist Order pursuant to Section 21C of the Securities Exchange Act of 1934.

We are exposed to certain asserted and unasserted potential claims. There can be no assurance that, with respect to potential claims made against us, we could resolve such claims under terms and conditions that would not have a material adverse effect on our business, our liquidity, our financial position or our operating results.

Item 4. Submission of Matters to a Vote of Security Holders.

Not applicable.

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PART II

Item 5. Market for the Registrant’s Common Stock, Related Stockholder Matters, and Issuer Purchases of Equity Securities.

Market Information

Our common stock is traded on the over-the-counter market and prices are quoted on the NASDAQ Global Market under the symbol “LSCC.”  The following table sets forth the low and high intraday sale prices for our common stock for the last two fiscal years, as reported by NASDAQ.

 

Holders

As of March 7, 2007, we had approximately 418 stockholders of record.

Dividends

The payment of dividends on our common stock is within the discretion of our Board of Directors. We intend to retain earnings to finance the growth of our business. We have never paid cash dividends.

Recent Sales of Unregistered Securities

None.

Issuer Purchases of Equity Securities

None.

Comparison of Total Cumulative Stockholder Return

The following graph shows the five-year comparison of cumulative stockholder return on our common stock, the S&P 500 Index and the Philadelphia Semiconductor Index (SOX) from December 2001 through December 2006. Cumulative stockholder return assumes $100 invested at the beginning of the period in our common stock, the S&P 500 and the Philadelphia Semiconductor Index (SOX). Historical stock prices performance is not necessarily indicative of future stock price performance.

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Lattice Cumulative Stockholder Return

COMPARISON OF 5 YEAR CUMULATIVE TOTAL RETURN*
Among Lattice Semiconductor Corporation, The S & P 500 Index
And The Philadelphia Semiconductor Index

*                    $100 invested on 12/31/01 in stock or index-including reinvestment of dividends.  Values stated as of the end of calendar years.

Copyright © 2007, Standard & Poor's, a division of The McGraw-Hill Companies, Inc. All rights reserved. www.researchdatagroup.com/S&P.htm

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Item 6. Selected Financial Data.

 

(1)          Effective January 1, 2006 the Company adopted SFAS No. 123(R) using the modified prospective transition method. For the fiscal year ended December 30, 2006, we recognized $3.6 million of stock-based compensation, of which $0.3 million was included in Cost of products sold, $1.9 million was included in Research and development and $1.4 million was included in Selling, general and administrative expense.

(2)          Upon the adoption of SFAS No. 123(R) effective January 1, 2006, stock compensation expense related to acquisitions (attributable to research and development activities) and previously classified as part of Amortization of intangible assets has been reclassified to Research and development expense. Such deferred stock compensation attributable to research and development activities was completely recognized as of April 1, 2006. As a result of the reclassification, Research and development expense includes $1.8 million, $3.4 million, $5.7 million and $3.0 million of amortization of deferred stock compensation expense for the fiscal years ended December 31, 2005, January 1 2005, January 3, 2004 and December 28, 2002, respectively.

(3)          Convertible notes include the amount in Zero Coupon Convertible Subordinated Notes due 2010 and Other current liabilities per the Consolidated Balance Sheet.

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Item 7. Management’s Discussion and Analysis of Financial Condition and Results of Operations.

Lattice Semiconductor Corporation (the “Company”) designs, develops and markets high performance programmable logic products and related software. Programmable logic products are widely used semiconductor components that can be configured by the end customer as specific logic circuits, and enable the end customer to shorten design cycle times and reduce development costs. Within the programmable logic market there are two groups of products—programmable logic devices (“PLDs”) and field programmable gate arrays (“FPGAs”)—each representing a distinct silicon architectural approach. Products based on the two alternative programmable logic architectures are generally optimal for different types of logic functions, although many logic functions can be implemented using either architecture. We believe that a substantial portion of programmable logic customers utilize both PLD and FPGA architectures. Our end customers are primarily original equipment manufacturers in the communications, computing, industrial, consumer, automotive, medical and military end markets.

Critical Accounting Policies and Estimates

Critical Accounting Policies are those that are both most important to the portrayal of a company’s financial condition and results and require management’s most difficult, subjective and complex judgments, often as a result of the need to make estimates about the effect of matters that are inherently uncertain. A description of our critical accounting policies follows.

Use of Estimates.   The preparation of financial statements in conformity with generally accepted accounting principles requires management to make estimates and assumptions that affect the reported amounts and classification of assets, such as accounts receivable, inventory and deferred income taxes and liabilities, such as accrued liabilities, income taxes and deferred income and allowances on sales to certain distributors, disclosure of contingent assets and liabilities at the date of the financial statements and the reported amounts of revenues and expenses during the fiscal periods presented. Actual results could differ from those estimates.

Revenue Recognition and Deferred Income.   Revenue from sales to customers is generally recognized upon shipment provided that persuasive evidence of an arrangement exists, the price is fixed or determinable, title has transferred, collection of resulting receivables is probable, there are no customer acceptance requirements and no remaining significant obligations. Certain of our sales are made to distributors under agreements providing price protection and right of return on unsold merchandise. Revenue and cost relating to such distributor sales are deferred until either the product is sold by the distributor or return privileges and price protection rights terminate, at which time related estimated distributor resale revenue, estimated effects of distributor price adjustments, and estimated costs are reflected in income. Revenue from software licensing was not material for the periods presented.

Beginning in fiscal 2006 we entered into arrangements with certain distributors to issue accounts receivable credit adjustments (“distributor advances”) to reduce the distributors’ working capital required to service our end customers. The distributor advances are for estimated future price discounts and are recorded as a reduction of Deferred income and allowances on sales to distributors. These arrangements are unsecured, bear no interest, are settled on a quarterly basis and are due upon demand. The distributor advances have no impact on revenue recognition.

Inventory.   We value inventory at the lower of cost or market on a quarterly basis. In addition, we write down unproven, excess and obsolete inventories to net realizable value. To value our inventory, we make a number of estimates and assumptions including market and economic conditions, product lifecycles and forecasted demand for our products. To the extent actual results differ from these estimates and assumptions, the balances of reported inventory and cost of products sold will change accordingly.

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Long-Lived Assets.   We account for our long-lived assets, primarily property and equipment and amortizable intangible assets, in accordance with Statement of Financial Accounting Standards (“SFAS”) No. 144, “Accounting for the Disposal of Long-Lived Assets,” which requires us to review the impairment of long-lived assets whenever events or changes in circumstances indicate that the carrying amount of an asset may not be recoverable. Impairment is determined by comparing the estimated undiscounted cash flows to the carrying amount. A loss is recorded if the carrying amount of the asset exceeds the estimated undiscounted cash flows. Intangible assets are generally being amortized over five years, and fifteen years for income tax purposes, on a straight-line basis.

Restructuring Charges.   Restructuring charges are recognized and recorded at fair value as incurred in accordance with SFAS No. 146, “Accounting for Costs Associated with Exit or Disposal Activities.” Restructuring costs include severance and other costs related to employee terminations, facility costs related to abandonment of various leased research and development sites, and other costs associated with the exit and disposal activities. As changes to these estimates occur in subsequent periods resulting from timing changes or other factors, we will record either an increase or decrease to the estimated costs previously recorded. It is possible that actual costs incurred in the future will differ from the amounts recorded at December 30, 2006.

Accounting for Income Taxes.   To report income tax expense related to operating results, we record current and deferred income tax assets and liabilities in our Consolidated Balance Sheet. In determining the value of our deferred tax assets, we make estimates of future taxable income. At the end of fiscal years 2006, 2005 and 2004, we have recorded full valuation allowances for all of our U.S. deferred tax assets due to uncertainties regarding their realization. At the end of fiscal years 2006 and 2005, we have recorded a partial valuation allowance against our foreign deferred tax assets. We had no foreign deferred tax assets at the end of fiscal 2004.

In addition, in determining the value of income tax liabilities we make estimates of the results of future examinations of our income tax returns by taxing authorities. We believe that we have adequately provided in our Consolidated Financial Statements for additional taxes that we estimate may result from these examinations. If these amounts provided prove to be more than what is necessary, the reversal of the reserves would result in tax benefits being recognized in the period in which we determine the liability is no longer necessary. If an ultimate tax assessment exceeds our estimate of tax liabilities, an additional charge to expense will result. See Note 8 and Note 13 to our Consolidated Financial Statements.

Stock-Based Compensation.   In the first quarter of 2006, we adopted “Share Based Payment—a revision of SFAS No. 123, Accounting for Stock-Based Compensation” (“SFAS No. 123(R)”), which requires the measurement at fair value and recognition of compensation expense for all share-based payment awards. Determining the appropriate fair-value model and calculating the fair value of employee stock options and rights to purchase shares under stock purchase plans at the date of grant requires judgment. We use the Black-Scholes option pricing model to estimate the fair value of these share-based awards consistent with the provisions of SFAS No. 123(R). Option pricing models, including the Black-Scholes model, also require the use of input assumptions, including expected volatility, expected life, expected dividend rate, and expected risk-free rate of return. The assumptions for expected volatility and expected life are the two assumptions that significantly affect the grant date fair value.

Upon the adoption of SFAS No. 123(R) effective January 1, 2006, stock compensation expense related to acquisitions (attributable to research and development activities) and previously classified as part of Amortization of intangible assets has been reclassified to Research and development expense. Such deferred stock compensation attributable to research and development activities was completely recognized as of April 1, 2006.

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Results of operations

Revenue

Revenue in fiscal 2006 increased to $245.5 million as compared to $211.1 million in fiscal 2005 primarily due to growth of New products and FPGA products as well as strength in the communications, consumer and military end markets. During fiscal 2006, total units sold increased by 16% while overall average selling price was relatively constant when compared to fiscal 2005. The increase in units sold was a result of overall growth in the programmable logic market along with increased market share.

Revenue in fiscal 2005 decreased to $211.1 million as compared to $225.8 million in fiscal 2004 primarily due to weakness in the communications, computing and industrial end markets.  During fiscal 2005, total units sold decreased by four percent and average selling price declined by two percent when compared to fiscal 2004.

The communications end market accounted for approximately 50% of our revenue in fiscal years 2006, 2005 and 2004. Accordingly, a significant portion of our revenue is dependent on the health of this end market. The communications end market weakened in the later portion of fiscal 2004, slowly improved throughout 2005 and the first half of 2006 before weakening in the later part of 2006.

Revenue by Product Line

From a product line viewpoint, in fiscal 2006 there was a 43% increase in FPGA units sold, partially offset by a 13% decrease in average selling price when compared to fiscal 2005. For PLD products in fiscal 2006, units sold increased 16%, partially offset by a one percent decrease in average selling price when compared to fiscal 2005.  PLD and FPGA product revenue decreased six percent and eight percent, respectively, for fiscal 2005 compared to 2004.

The composition of our revenue by product line for fiscal years 2006, 2005 and 2004 was as follows (dollars in thousands):

 

Revenue by Product Classification

Revenue for New, Mainstream and Mature products, increased 86%, 15% and three percent, respectively, for fiscal 2006 compared to 2005. The fiscal 2005 decrease in units sold was predominantly attributable to lower sales of Mainstream and Mature products due to reduced end market demand while the decrease in average selling price was primarily due to product mix. Among other things, future revenue growth is dependent on overall economic conditions for our industry and market acceptance of our New products.

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The composition of our revenue by product classification for fiscal years 2006, 2005 and 2004 was as follows (dollars in thousands):

*                    Product classification

New:		LatticeSC, LatticeECP2/M, LatticeECP, LatticeXP, MachXO, FPSC, ispXPLD, ispGDX2, Power Manager, ispClock
Mainstream:		ispMACH 4000/Z, ispXPGA, ispGDX/V, ispMACH 4/LV, ispLSI 2000V, ispLSI 5000V, ispMACH 5000VG, Software and IP
Mature:		ORCA 2, ORCA 3, ORCA 4, ispPAC, ispLSI 8000V, ispMACH 5000B, ispMACH 2LV, ispMACH 5LV, all 5-Volt CPLDs, all SPLDs

 

Beginning in fiscal 2006 we reclassified our New, Mainstream and Mature product categories to better reflect our current product portfolio. The New product category was narrowed, and as such several products were removed from our New product category and are now classified as Mainstream. As part of the change to product categories, we also reclassified certain products from Mainstream to Mature. Prior period ratios have been recalculated to reflect these new product category classifications. Newly released product families have also been added to the New product classification. We periodically update our product classifications and plan to update our classifications again in fiscal 2007.

Revenue by Geography

Revenue from export sales as a percentage of total revenue was 80% for fiscal 2006, 77% for 2005 and 71% for 2004. Export revenue as a percentage of overall revenue increased in fiscal 2006 compared to 2005 and 2004 due to relatively more favorable business conditions in Asia and a continuing trend towards outsourcing of manufacturing by North American customers.

The composition of our revenue by geographical location of our direct and indirect customers is as follows (in thousands):

 

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Stock-Based Compensation Expense

Effective January 1, 2006, we adopted SFAS No. 123(R) using the modified prospective transition method and therefore have not restated results for prior periods. Our results of operations in fiscal 2006 were impacted by the recognition of non-cash expense related to the fair value of our stock-based payment awards. For the year ended December 30, 2006 we recognized $3.6 million of stock-based compensation expense, of which $0.3 million was included in Cost of products sold, $1.9 million was included in Research and development and $1.4 million was included in Selling, general and administrative expense. See Note 11 to the Consolidated Financial Statements in Item 8, which is incorporated herein by reference.

Gross Margin and Operating Expenses

Key elements of our Consolidated Statement of Operations, expressed as a percentage of revenue, were as follows:

(1)          Our Statement of Operations includes the effect of stock-based compensation as quantified in Note 11 to the Consolidated Financial Statements in Item 8.

Our gross margin percentage was 57% for fiscal 2006, 55% for 2005 and 57% for 2004. The increase in gross margin percentage from fiscal 2005 to 2006 reflects revenue growth in Mainstream products, which had an improved margin in fiscal 2006 versus 2005 due to yield enhancements and cost reductions. The decline in gross margin percentage from fiscal 2004 to 2005 resulted primarily from revenue growth in New products, which typically carry an initial lower gross margin and a decline in revenue from Mature products, which typically carry a higher gross margin. Additionally, in the fourth quarter of fiscal 2005 we initiated a last-time buy program to recognize the obsolescence of certain Mature products, resulting in a charge to Cost of products sold to write down excess inventory.

Research and development expense was $82.0 million for fiscal 2006 compared to $97.2 million for 2005 and $94.4 million for 2004. Research and development expenses consist primarily of personnel, masks, engineering wafers, third-party design automation software, assembly tooling and qualification expenses. The decrease in expense in fiscal 2006 compared to 2005 is primarily a result of the restructuring plan implemented during the fourth quarter of fiscal 2005 (“2005 restructuring plan”), which is further described below.  In addition, the decrease also resulted from elimination of stock compensation expense related to previous acquisitions.  Although we experienced a considerable decline in research and development expense during fiscal 2006 compared to 2005, we believe that a continued commitment to research and development is essential in order to maintain product leadership and provide innovative new product offerings, and therefore we expect to continue to make significant future investments in research and development. As we continue to move to more advanced process technologies such as 90nm and beyond, mask and engineering wafer costs are becoming increasingly more expensive and will therefore increasingly represent a greater proportion of total research and development expenses. The increase in fiscal 2005 when compared to the prior year resulted primarily from mask and engineering wafer costs for the completion of new products, and to a lesser extent, personnel related costs.

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Selling, general and administrative expense was $58.5 million in fiscal 2006, $57.5 million in 2005 and $53.8 million in 2004. The increase in fiscal 2006 compared to 2005 is due to a number of factors including a reduction of sublease income, which is recorded as an offset to Selling, general and administrative expense, recognition of stock compensation, increased commission and compensation related expense and the 2005 restructuring plan, which is further described below. These increases were mostly offset by a $6.5 million reduction in legal expenses in fiscal 2006 compared to 2005. The fiscal 2005 increase compared to 2004 was primarily due to legal expenses related to shareholder class action suits, an SEC informal inquiry, shareholder derivative suits, a Special Litigation Committee investigation and Audit Committee investigation, all of which were resolved at December 30, 2006. Legal expenses related to these matters resulted in a total charge of $6.3 million during fiscal 2005 and $1.6 million in 2004. These increases in legal expenses were partially offset by decreases primarily in consulting services, sales related expenses and other miscellaneous items.

Amortization of intangible assets is related to our 2002 acquisition of the FPGA business of Agere Systems Inc. and of Cerdelinx and our 1999 acquisition of Vantis Corporation. Amortization expense was $10.8 million in fiscal 2006, $14.4 million in 2005 and $43.8 million in 2004. Amortization expense in fiscal 2006 decreased as a portion of the intangible assets acquired in the Agere acquisition became completely amortized. The decrease in amortization expense in fiscal 2005 compared to 2004 was attributable to completion of amortization of certain intangible assets from the Vantis and Agere acquisitions.

During the fourth quarter of fiscal 2005, we initiated and substantially completed the 2005 restructuring plan to reduce operating expenses and improve efficiency. The restructuring encompassed three major components—a streamlining of research and development sites, a voluntary separation program for certain employees and an organizational consolidation within the Company’s largest design center. These actions did not significantly impact our product direction or product roll-out strategy. In the fourth quarter of fiscal 2005, the Company recorded an initial restructuring charge of $11.9 million which included $6.1 million of severance related costs, $2.5 million of lease related costs and $3.3 million of other costs, including a $2.7 million write-off of an intellectual property license. Restructuring charges decreased significantly to $0.3 million in fiscal 2006. All of our restructuring accruals at December 30, 2006 are related to the 2005 restructuring plan.

Effective January 1, 2006, the Company realigned certain departments and job responsibilities. As a result, a portion of the historic cost center allocations have been realigned between Selling, general and administrative and Research and development to reflect our operations following the 2005 restructuring plan. The realignment reduced fiscal 2006 Research and development expense by approximately $3.1 million, which was primarily offset by a corresponding increase in Selling, general and administrative expense.

The following table displays the current estimate for each major type of cost associated with the 2005 restructuring plan (in thousands):

 

Included in expense amounts for the year ended December 31, 2005 are disposals of leasehold improvements and fixed assets totaling $0.3 million and $0.2 million, respectively. The above restructuring charges are based on estimates that are subject to change. Lease charges change based on our ability to

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either generate sublease income or terminate lease obligations at the amounts estimated, and are dependent upon lease market conditions at the time we negotiate the potential lease arrangements. Variance from these estimates could alter our ability to achieve anticipated expense reductions in the planned timeframe and modify our expected cash outflows and working capital.

Although the 2005 restructuring plan was substantially completed during the fourth quarter of fiscal 2005, we cannot be certain as to the actual amount of any remaining restructuring charges or the timing of their recognition for financial reporting purposes, though the amount of future charges in addition to the current reserve is not expected to be significant.

Interest and Other Income (expense), net

Interest income was $13.0 million in fiscal 2006, $8.5 million in 2005 and $4.4 million in 2004. The increases in fiscal 2006 compared to 2005, and in 2005 compared to 2004, are primarily attributable to higher interest rates.

Other income, net, was $4.0 million in fiscal 2006, $8.6 million in 2005 and $7.0 million in 2004. For fiscal 2006, Other income, net, consisted of a $1.6 million gain on sale of UMC common stock and a $2.4 million gain on extinguishment of Zero Coupon Convertible Subordinated Notes due in 2010 (“Convertible Notes”), net of $0.1 million of amortization of Convertible Note issuance costs and other costs. For fiscal 2005, Other income, net, consisted primarily of a $4.3 million gain on sale of UMC common stock and a $4.9 million gain on extinguishment of Convertible Notes, net of $0.9 million amortization of Convertible Note issuance costs and other costs. For fiscal 2004, Other income, net, consisted of a $6.1 million gain on sale of UMC common stock and a $2.8 million gain on extinguishment of Convertible Notes, net of $1.9 million amortization of Convertible Note issuance costs and other costs. To the extent market conditions allow, we may make similar extinguishments of our Convertible Notes and sales of UMC common stock in the future.

We are paying foreign income taxes, which are reflected in the Consolidated Statement of Operations, and are primarily related to the cost of operating our offshore research and development and sales subsidiaries. We are not currently paying federal or state income taxes and do not expect to pay such taxes until the benefits of our tax net operating losses are fully utilized. We accrue interest expense on our tax contingency reserve.

Liquidity and Capital Resources

Financial Condition (Sources and Uses of Cash)

Fiscal 2006 compared to 2005

Operating

Net cash used in operating activities decreased by $5.5 million in fiscal 2006 as compared to 2005. The change is primarily related to recognition of net income in fiscal 2006 compared to a net loss in 2005. This was offset primarily by an increase in inventories during fiscal 2006, compared to a decrease in 2005 due primarily to increased inventories related to New products in fiscal 2006, while reduced starts and fewer receipts of wafers at the end of fiscal 2005 reduced the 2005 inventory balance. Also contributing to the offset in fiscal 2006 was cash used for an advance payment to Fujitsu compared to the lesser payment made in 2005. In addition, while fiscal 2005 includes the charge related to the 2005 restructuring plan, the majority of the cash payments related to the 2005 restructuring plan were made in fiscal 2006.

Investing

Net cash provided by investing activities decreased by $11.1 million for fiscal 2006 as compared to 2005.  The change is due primarily to a decrease in the sale of equity securities (principally UMC common stock) offset by an increase in net proceeds from short-term investments. Net proceeds from the sale of equity securities (principally UMC common stock) totaled $13.3 million for fiscal 2006 as compared to

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$27.5 million for 2005. Net proceeds from short-term investments totaled $32.1 in fiscal 2006 compared to $26.6 million in 2005. Further, capital expenditures were greater in fiscal 2006, totaling $13.7 million compared to $11.3 million in 2005.

Financing

Net cash used in financing activities decreased $12.2 million for fiscal 2006 as compared to 2005. The decrease is due primarily to the use of $21.6 million to extinguish our Convertible Notes in fiscal 2006 compared to $30.2 million in 2005. Further, net proceeds from the issuance of common stock for fiscal 2006 increased $4.2 million over 2005.

Fiscal 2005 compared to 2004

Operating

Net cash used by operating activities was $20.0 million in fiscal 2005, compared to $6.0 million of cash provided by operating activities in 2004. The change is primarily related to the change in net income after excluding the effect of non-cash charges, and a reduction in accounts receivable collections. This decrease in cash provided by operations was partially offset by an increase in the receipt of wafers credited to wafer advances in fiscal 2005 over 2004, and the timing of payments related to the 2005 restructuring plan benefited cash flow from operations in fiscal 2005.

Investing

Net cash provided by investing activities increased by $32.9 million for fiscal 2005 as compared to 2004.  The change is due primarily to an increase in net proceeds from short-term investments offset by the decrease in the sale of equity securities (principally UMC common stock). Net proceeds from short-term investments totaled $26.6 million in fiscal 2005 compared to net purchase of short-term investments of $9.0 million in 2004. Net proceeds from the sale of equity securities (principally UMC common stock) totaled $27.5 million for fiscal 2005 as compared to $29.6 million for 2004. Further, capital expenditures increased in fiscal 2005, totaling $11.3 million compared to $10.7 million in 2004.

Financing

Net cash used in financing activities increased $22.0 million for fiscal 2005 as compared to 2004. The increase is due primarily to the use of $30.2 million to extinguish our Convertible Notes in fiscal 2005 compared to $12.0 million in 2004. Further, net proceeds from the issuance of common stock for fiscal 2005 decreased $3.1 million compared to 2004.

Liquidity

At December 30, 2006 our principal source of liquidity was $233.2 million of cash and marketable securities, which was $31.0 million less than the balance of $264.2 million at December 31, 2005. Working capital decreased by $50.1 million to $218.3 million at December 30, 2006 from $268.4 million at December 31, 2005. This decrease was the result of $21.6 million paid to extinguish Convertible Notes, an advance payment of $37.5 million to Fujitsu and capital expenditures of $13.7 million.

We believe that our existing liquid resources and expected cash generated from future operations, combined with wafer credits from foundries and our ability to borrow additional funds, will be adequate to meet our operating and capital requirements and obligations for the next 12 months. Included in such anticipated obligations at December 30, 2006 was the advance payment to Fujitsu of $37.5 million that was made in January 2007. This payment represents the final installment to complete the unsecured advance payments of $125.0 million to Fujitsu for prepaid wafers. The advance payments will be returned to us in the form of wafer credits or other repayment, subject to the right of either party to terminate the agreement upon the occurrence of certain events. As of December 30, 2006, $3.2 million had been returned to us in the form of wafer credits, and we expect an additional $20.5 million to be returned to us in the form of wafer credits during the next twelve months. If we do not use all of our wafer credits by December 31, 2008 we may request a refund of the unused amount of the advance payment. The repayment obligation of Fujitsu is unsecured.

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From 2003 through December 30, 2006, we paid an aggregate of $78.0 million to extinguish $90.4 million principal amount of Convertible Notes, which are due July 1, 2010. In addition, in the first quarter of fiscal 2007 we paid $19.6 million to extinguish $20.5 million in principal amount of Convertible Notes. From time to time we will assess our liquidity and capital resources, and overall economic and market conditions, and may repurchase additional Convertible Notes prior to their due date. While the Convertible Notes are due for payment in 2010, unless previously redeemed, purchased, repurchased or converted, holders of the Convertible Notes have a right to require payment of the Convertible Notes on July 1, 2008. At December 30, 2006, $109.6 million principal amount of the Convertible Notes remain outstanding.

We may in the future seek new or additional sources of funding. In addition, in order to secure additional wafer supply, we may from time to time consider various financial arrangements including equity investments, advance purchase payments, loans, or similar arrangements with independent wafer manufacturers in exchange for committed wafer capacity. To the extent that we pursue any such additional financing arrangements, additional debt or equity financing may be required. There can be no assurance that such additional financing will be available when needed or, if available, will be on favorable terms. Any future equity financing will decrease existing stockholders’ equity percentage ownership and may, depending on the price at which the equity is sold, result in dilution.

Contractual Obligations

The following table summarizes our significant contractual cash obligations at December 30, 2006 (in thousands):

(1)          Certain of our facilities and equipment are leased under operating leases, which expire at various times through 2013. Rental expense under the operating leases was $5.1 million, $8.6 million and $5.9 million for fiscal years 2006, 2005 and 2004, respectively. Included in the table above for operating leases are the properties that were vacated as part of our 2005 restructuring plan. For fiscal 2007, future minimum sublease receipts net of such payments, based on agreements in place at December 30, 2006, total $0.1 million. In the first quarter of 2007 we entered into a sublease agreement for a portion of the research and development facility in San Jose, California and for the vacated premises in Austin, Texas.

(2)          This column excludes amounts already recorded on our Consolidated Balance Sheet as current liabilities at December 30, 2006.

(3)          This represents our obligation to make the final payment pursuant to the Advance Payment and Purchase Agreement with Fujitsu Limited and is included in Accounts payable and accrued expenses on the Consolidated Balance Sheet at December 30, 2006.

(4)          On July 1, 2008, holders have the option to require us to purchase all or a portion of their Convertible Notes in cash at 100% of the principal amount of the Convertible Notes.

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In December 2000, our Board of Directors authorized management to repurchase up to five million shares of our common stock. As of December 30, 2006, we had repurchased 1,136,000 shares at an aggregate cost of $20.0 million. There were no repurchases of common stock in fiscal years 2004, 2005 or 2006. Our only significant operating leases, apart from those accrued for in the 2005 restructuring plan, are for our facilities in San Jose, California and Bethlehem, Pennsylvania. Our lease in San Jose expires in December of 2008. Annual rent is $4.0 million and increases 3% annually. Our lease in Bethlehem expires in August of 2009. Annual rent is $0.8 million and increases 3% annually. Leasehold improvements are amortized over the shorter of the non-cancelable lease term or the estimated useful life of the assets.

On September 10, 2004, we entered into an Advance Payment and Purchase Agreement (the “Fujitsu APP Agreement”) with Fujitsu Limited (“Fujitsu”), pursuant to which we advanced $125.0 million to Fujitsu in support of the development and construction of a 300mm wafer fabrication facility in Mie, Japan. The initial two payments of $25.0 million each were made in October 2004 and January 2005, and a third payment of $37.5 million was made in November 2006. The final payment of $37.5 million was accrued and recorded at December 30, 2006 and was paid in January 2007.

During the third quarter of fiscal 2006, we entered into an amendment (“Amendment”) to the Fujitsu APP Agreement. Prior to the Amendment, our $125.0 million advance was to be credited against the purchase price of 300mm wafers received from Fujitsu. The Amendment permits us to also credit the advance against the purchase price of 200mm wafers. The Fujitsu APP Agreement will continue until the full amount of the advance payment has been returned to us in the form of wafer credits or other repayment, subject to the right of either party to terminate the agreement upon the occurrence of certain events. Prior to the Amendment, we could request a refund of the unused amount of the advance payment if we have not used all of our wafer credits by December 31, 2007. Pursuant to the Amendment, we may request a refund of the unused amount of the advance payment if we have not used all of our wafer credits by December 31, 2008. The repayment obligation of Fujitsu is unsecured.

New Accounting Pronouncements

In March 2006, the Emerging Issues Task Force reached a consensus on Issue No. 06-03 “How Taxes Collected from Customers and Remitted to Government Authorities Should be Presented in the Income Statement (That Is, Gross versus Net Presentation)” (“EITF No. 06-03”). The Company is required to adopt the provisions of EITF No. 06-03 beginning with fiscal year 2007. The Company does not expect the provisions of EITF No. 06-03 to have a material impact on the Company’s Consolidated Balance Sheet, Statement of Operations or Statement of Cash Flows.

In June 2006, the Financial Accounting Standards Board (“FASB”) issued FASB Interpretation No. 48, “Accounting for Uncertainty in Income Taxes - an interpretation of FASB Statement No. 109” (“FIN No. 48”). This Interpretation prescribes a recognition threshold and measurement attribute for the financial statement recognition and measurement of a tax position taken or expected to be taken in a tax return, and provides guidance on derecognition, classification, interest and penalties, accounting in interim periods, disclosure and transition. This Interpretation is effective for fiscal years beginning after December 15, 2006. We are currently evaluating the impact of FIN No. 48 on the Company’s Consolidated Balance Sheet, Statement of Operations and Statement of Cash Flows.

In September 2006, FASB issued SFAS No. 157, “Fair Value Measurements” (“SFAS No. 157”), which defines fair value of certain assets and liabilities, establishes a framework for measuring fair value and expands disclosures about fair value measurements. This statement does not require any new fair value measurements, but may change current practice for certain entities. This statement is effective for financial statements issued for fiscal years beginning after November 15, 2007 and interim periods within those years. We are currently assessing the impact of SFAS No. 157 on the Company’s Consolidated Balance Sheet, Statement of Operations and Statement of Cash Flows.

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In February 2007, the FASB issued SFAS No. 159, “The Fair Value Option for Financial Assets and Financial Liabilities” (“SFAS No. 159”). SFAS No. 159 permits companies to choose to measure certain financial instruments and certain other items at fair value. The standard requires that unrealized gains and losses on items for which the fair value option has been elected be reported in earnings. SFAS No. 159 is effective for the Company beginning in the first quarter of fiscal year 2008, although earlier adoption is permitted. We are currently assessing the impact of SFAS No. 159 on the Company’s Consolidated Balance Sheet, Statement of Operations and Statement of Cash Flows.

Off-Balance Sheet Arrangements

As of December 30, 2006, we did not have any off-balance sheet arrangements, as defined in Item 303(a)(4)(ii) of SEC Regulation S-K.

Item 7A. Quantitative and Qualitative Disclosures About Market Risk.

As of December 30, 2006 and December 31, 2005 our investment portfolio consisted of fixed income securities of $226.4 million and $258.7 million, respectively. As with all fixed income instruments, these securities are subject to interest rate risk and will decline in value if market interest rates increase. If market rates were to increase immediately and uniformly by 10% from levels at the years ended December 30, 2006 and December 31, 2005, the decline in the fair value of our portfolio would not be material. Furthermore, we have the ability to hold our fixed income investments until maturity and, therefore, we would not expect to recognize such an adverse impact in our results from operations or statement of cash flows.

The fair market value of the Convertible Notes is subject to interest rate risk and market risk due to the convertible feature of the Convertible Notes and the fair market value of the Company’s common stock. Generally the fair market value of fixed interest rate debt will increase as interest rates fall and decrease as interest rates rise. The interest and market value changes affect the fair market value of the Convertible Notes, but changes in the fair market value of Convertible Notes do not impact our financial position, cash flows or results of operations. At December 30, 2006 the fair value of the Convertible Notes was $104.8 million based on recent sales.

We have international subsidiary and branch operations. Additionally, we sell products to Japanese customers denominated in yen. We are therefore subject to foreign currency exchange rate exposure. To minimize foreign exchange risk related to yen-based net assets on our Consolidated Balance Sheet, on August 11, 2004, we entered into an agreement with a bank under the terms of which we can borrow up to $6.0 million in Japanese yen in a revolving line of credit arrangement. Outstanding borrowing is collateralized by marketable securities. Interest on outstanding borrowing is based on the Japanese LIBOR Fixed Rate, and averaged 1.23% for the year ended December 30, 2006. Outstanding borrowing at December 30, 2006 was $5.3 million. This arrangement can be terminated at any time by either party.

We are exposed to equity price risk due to our equity investment in UMC (see Note 4 to our Consolidated Financial Statements). Neither a 10% increase nor a 10% decrease in equity price related to this investment would have a material effect on our Consolidated Financial Statements as of the years ended December 30, 2006 or December 31, 2005. We have not attempted to reduce or eliminate this equity price risk through hedging or similar techniques. As a result, sustained changes in the market price of UMC common stock could impact our financial results. To the extent that the market value of our UMC common stock experiences deterioration for an extended period of time, our operating results could be adversely affected.

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Item 8. Financial Statements and Supplementary Data.

Index to Consolidated Financial Statements and Consolidated Financial Statement Schedule

 

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LATTICE SEMICONDUCTOR CORPORATION
CONSOLIDATED BALANCE SHEET
(in thousands, except share and par value amounts)

 

The accompanying notes are an integral part of these Consolidated Financial Statements.

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